The present invention relates generally to integrated circuit devices, and more specifically to functional failures associated with integrated circuit device process-related manufacturing defects.
As Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) technologies have quickly advanced in the past decade, the size, configuration, and complexity of VLSI and ULSI integrated circuit devices have increased and improved at a correspondingly fast rate. Application Specific Integrated Circuit (ASIC) Sea-of-Gate devices, characterized by a vast number of transistors manufactured according to the same process with no customer personalization, have seen especially meaningful advancements. For instance, the typical die size of ASIC Sea-of-Gate devices has increased from 300 kmil.sup.2 to 700 kmil.sup.2, gate count capability has increased from 2,000 to 800,000 gates, the number of conductor layers has increased from 3 to 5 layers, the number of signal pins has increased from 100 to 400 pins, while the transistor size has decreased from 3 .mu.m to 0.5 .mu.m, all within the last ten years. Together, these improvements represent an increased complexity on the order of four magnitudes when comparing ASIC Sea-of-Gate devices of today with those of 1984.
In addition to this increased complexity, the design specifications of Sea-of-Gate devices are typically proprietary and thus not shared with the manufacturer of Sea-of-Gate devices. This lack of knowledge serves to further complicate the device manufacturer's debugging of process-related problems such as interconnect problems with contacts and vias, conductor layer problems with the polysilicon and metal lines, and insulator problems with the gate oxide and interlevel dielectric, all of which may cause low yield. And, in reality, the increasing complexity and lack of knowledge of Sea-of-Gate devices have cost the manufacturer an enormous amounts of resources, equipment, and time with regard to the functional failure analyses which are performed in response to line yield fallout, qualification failures, and customer device returns. The analysis requires both a high level of engineering expertise and state-of-the-art test equipment, such as high cost device testers. Additionally, even when these resources are brought to bear, it may be weeks before the functional failure analysis is complete and test results become available.
Examination of a typical process flow and the required time and equipment may help to illustrate the enormous amount of resources which must currently be dedicated to identifying and assessing process-related functional failures of an integrated circuit device. Referring to FIG. 1, a flow chart of a representative process currently used for functional failure analysis is shown. Packaging of the integrated circuit device typically takes one to four days. This is followed by modification of the device test program for failure analysis of the device which typically takes from one to two days. This is followed by the actual functional analysis of the device where any failures are only isolated to a cell which may have anywhere from two to eight transistors. Actual functional analysis of the device requires the use of an expensive tester and E-Beam Prober, and can take from two to ten days to complete. Next, DC (Direct Current) analysis of the device is performed; DC analysis requires the use of a mechanical prober as well as an emission microscope, and typically takes up to one day. Thus, it can be seen that functional failure analysis, as is currently done in the art, can take a total of anywhere from five to seventeen days and requires the use of expensive equipment, such as testers and probers. Additionally, typical functional analysis only pinpoints the cause of functional failure to a cell which may have as many as 8 transistors. Thus, it is currently difficult to ascribe process-related failures to a small number of transistors with certainty.
Thus, there is a current need in the art to decrease the quantity and quality of resources utilized during functional failure analysis of integrated circuit device, such as Sea-of-Gate ASIC devices. This means decreasing the level of technical expertise, the use of high cost equipment, and the time required to isolate process-related defects of integrated circuit devices.